1. Field of the Invention
The invention relates to an architecture for a Reed Soloman decoder with improved efficiency.
2. Background
Reed Soloman codes are error-correcting codes used to improve the robustness of communication and storage systems. A data stream, consisting of k m-bit symbols, is typically protected against errors by appending r m-bit redundant symbols, so that the concatenated stream of n=k+r m-bit symbols forms a Reed Solomon codeword. Some symbols of the transmitted or stored codeword may be erroneous when recovered, and if the number of erroneous symbols is small enough, they can be found and corrected by a Reed Solomon decoder.
In some systems, the recovery circuitry generates a measure of each symbol's reliability as the recovered symbols are produced. If a symbol is regarded as unreliable, an erasure flag is generated to indicate its location to the Reed Solomon decoder. If s flagged and t unflagged erroneous symbols are recovered, a Reed Solomon decoder designed to process these erasure flags is capable of correcting the errors if 2t+s<=r . We refer to such a decoder as an error-and-erasure decoder.
In other systems the recovery circuitry does not process erasure flags, and such a decoder is therefore referred to as an error-only decoder. If t erroneous symbols (i.e., t errors) are recovered, an error-only Reed Solomon decoder is capable of correcting the errors if 2t<=r.
A typical Reed-Solomon error-correction system utilizes an encoder and decoder. The encoder inputs the k data symbols and appends the r redundant symbols in such a manner that the n symbols of a Reed-Solomon codeword can be regarded a the coefficients of a polynomial of degree n−1, which is a multiple of a generator polynomial of degree r−1. The roots of the generator polynomial are consecutive powers of a so-called primitive element, as it is commonly known in the literature, which is commonly referred to as α. These roots are{αIr0, αIr0+1, αIr0+2, . . . , αIr0+r−1},where Ir0 is an arbitrary logarithm in base α of the first root. In transmission or storage, some of the codeword symbols may be corrupted when received at the decoder.
A typical decoder architecture consists of three processing units. The first is referred to here as a syndromer, whose purpose is to calculate the so-called syndromes, as they are known in the literature, from the received vector. The syndromes are the coefficients of the Fourier transform of an error vector that the syndromer computes from the received vector. The syndromer typically requires one clock cycle per recovered symbol. The second is referred to here as a polynomial determining unit (PDU), and typically dominates the VLSI area of the decoder. The PDU determines various polynomials from the syndromes, depending upon the algorithm employed, including an error locator polynomial. The third processing unit is referred to here as a Chien searcher, which also typically requires one clock cycle per recovered symbol. The function of the Chien searcher is to find roots of the error locator polynomial, in order to locate the errors.
For high throughput, a PDU architecture is desired which can process a Reed Solomon codeword within a number of clock cycles equal to the number of symbols in a codeword, n. Early Reed-Solomon decoders utilized a single centralized Galois Field multiplier as part of a specialized arithmetic logic unit to perform the PDU functions. In this case, the problem of determining the polynomials from the syndromes is proportional in multiplications to the square of t, denoted O(t2), where t is the number of errors to be corrected. However, as the maximum number of errors, tmax, to be corrected has grown, the number of clock cycles to perform the PDU functions in these early implementations has exceeded n. Therefore, the focus today is on PDU architectures which utilize O(t) parallel multipliers and require O(t) clock cycles to determine the polynomials.
Berlekamp and Massey described algorithms for decoding Reed Solomon codes by determining certain polynomials. Although these algorithms have been slightly refined over time, they are still generally referred to in the literature as the Berlekamp-Massey algorithm. Typical implementations of the Berlekamp-Massey algorithm use the syndromes to determine an error locator polynomial, Λ(z) , and an error evaluator polynomial, Ω(z). As described by Berlekamp, the calculation of these two polynomials uses two additional scratch polynomials, A(z) and B(z). Each of the polynomials is approximately of degree t.
Later, Blahut described a method of determining Λ(z) from the syndromes using only the scratch polynomial B(z). Ω(z) was then determined in an additional step, convolving the syndrome polynomial S(z) with the locator polynomial, i.e., Ω(z)=S(z)·Λ(z). Further, Horiguchi showed that it is not necessary to determine the polynomial Ω(z); the errors can be directly determined from Λ(z) and one of the scratch polynomials used to produce it, B(z). Berlekamp's storage of two polynomials or Blahut's additional convolution can be eliminated to increase efficiency.
Feng revised Horiguchi's algorithm to make it more regular and suitable for VLSI implementation. To achieve this, Feng reformulated the algorithm and used a special circuit to calculate a scaling factor, Bp. This was done to prevent an overflow in the scratch polynomial B(z). An advantage of Feng's architecture is that the storage for iterative development of various polynomials is minimized, where the total storage is r m-bit registers used to hold the syndromes, tm-bit registers used to hold iterative solutions for Λ(z), and t m-bit registers used to hold iterative solutions for B(z), for a total of approximately 4tm registers in the polynomial determination unit. A disadvantage of Feng's architecture is that it uses 3t multipliers, and these multipliers dominate the VLSI area of the PDU.
Fredrickson described a PDU architecture which used approximately 2t multipliers in a shared fashion for reduced area while retaining approximately the same iteration time as Feng. The overall area and hence efficiency was improved, but the storage requirements for polynomials was larger than in Feng's architecture.